In recent years, with remarkable progress of high speed operation and high density integration of a semiconductor device, miniaturization of elements, especially, a gate insulating film of a field effect transistor (FET) has become rapidly thin. The thin gate insulating film is easy to be broken. For this reason, a technique related to a protection device is applied to protect the semiconductor device from electrostatic discharge (ESD) before the gate insulating film of the FET is broken down.
With decrease in a power supply voltage and reduction of the gate insulating film in thickness, design of the electrostatic protection device has become difficult. It is required that the electrostatic protection device operates at a snap-back voltage “Vh” after snap-back following an “ON” state, and the snap-back voltage is higher than a power supply voltage, and is lower than a breakdown voltage of the gate insulating film and a circuit breakdown voltage (junction breakdown) “Vo”. A difference between the voltage “Vh” and the voltage “Vo” decreases with miniaturization of the element, resulting in decrease in a design margin of the electrostatic protection device.
Under such a situation, an electrostatic protection circuit using an electrostatic protection device which does not perform a snap-back operation has been proposed. As such an electrostatic protection circuit, an electrostatic protection device is configured by serially connecting PN-junction elements in multiple stages between two terminals so as to be biased in a forward direction in a normal operation. In this configuration, although the so-called snap-back operation is not performed, the voltage corresponding to the snap-back voltage “Vh” of the conventional electrostatic protection device is determined as a summation of ON voltages of the PN-junction elements in a forward direction bias which is nearly equal to built-in potential (hereinafter, to be simply referred to as a forward bias voltage), and a product of an ESD current and a summation of equivalent resistances of the PN-junction elements (i.e. effective resistances) must be equal to or smaller than the voltage “Vo”. This is simply expressed by a following equation (1):Vdd<n×Vf<n×r×Iesd<Vo   (1)where Vf is the forward bias voltage, r is the equivalent resistance at a forward bias, Iesd is a current at electrostatic discharge, n is the number of PN-junction elements, and Vdd is the power supply voltage or a signal voltage in the normal operation. Usually, in consideration of leakage current suppression (α term) at the forward bias (especially at high temperature) and manufacturing variation (β term), the electrostatic protection device is designed to satisfy a following equation:Vdd+α<n×Vf<n×r×Iesd<Vo−β  (2)
Conventionally, in a bulk MOSFET process, the PN-junction element is formed as a junction between a diffusion layer and a well. As a matter of course, a structure such as a PN-junction in butted diffusion layer exists. However, in the PN-junction of the butted diffusion layer, the junction between a well and a substrate exists in a bottom surface of the diffusion layer. In the bulk MOSFET, the forward bias voltage of the PN-junction is determined based on an impurity concentration in the well/substrate.
When performing an application test of electrostatic discharge voltage Vesd [V] in an HBM test, the current Iesd in the equation (1) is:Iesd≈Vesd/1500 [A](in the HBM test, the resistance of 1.5 KΩ is inserted between the element and a test apparatus). It is required that a whole of PN-junction elements does not break down when this current flows.
To satisfy the equation (1) with respect to the voltage Vo, that is, to pass the HBM test applied with the voltage Vesd [V], the resistance R of the whole of the PN-junction elements is approximately expressed as:R≈Vo/Iesd=1500×Vo/Vesd   (3)At this time, using the number n of elements which satisfies the following relation:n<R/r, the electrostatic protection device is designed.
However, since the resistance r varies depending on a current value, the value of the resistance r cannot be simply determined. Further, the effective resistance of the whole of PN-junction elements can be changed by changing its size. When the PN-junction elements having a large value of r are used, the effective resistance can be adjusted by increasing the size of the PN-junction elements. Generally, the resistance per PN-junction perimeter or PN-junction area is measured and necessary size is determined to satisfy the equation (1) or the equation (2). For this reason, the resistance r has a relatively large design freedom. As a matter of course, since an increase in the size of the protection device leads to an increase in chip size, care should be taken.
In miniaturization of a MISFET (MOSFET), various types of SOI structure FET have been proposed in place of an ordinary bulk MISFET. A planar SOIFET and a FinFET have been developed as the SOI structure FET. The SOI structure FET has superior electrical characteristics to the bulk MISFET.
However, generally, from the viewpoint of electrostatic protection, the SOI structure FET has a lower breakdown voltage against electrostatic discharge (hereinafter to be referred to as ESD endurance) than the bulk MISFET. The SOI structure FET is formed on an insulating film, resulting in a poor heat radiation characteristic. For this reason, when the SOI structure FET is used as a protection device, the ESD endurance lowers.
Under such a situation, with miniaturization of the element, the gate insulating film of the MISFET is made thin due to a low power supply voltage, so that the breakdown voltage is lowered. As a result, an operation voltage range (required voltage-current characteristic) of the electrostatic protection device has been narrowed. An optimum electrostatic protection device in a semiconductor device having the SOI structure FET is required.
Patent literature 1 discloses an example of a configuration that the PN-junction elements of the protection device in the SOI structure device are connected in a forward bias in the ordinary operation.
Diodes 1060 to 1079 in FIG. 10 of the patent literature 1 are biased in the forward direction in the ordinary operation. In this example, the forward bias voltage (described as a forward turn-on voltage in the specification) of each of the diodes 1060 to 1079 is described to be about 0.7V. In other words, it can be considered that the diodes 1060 to 1079 have the same structure. When an applied voltage is larger than the power supply voltage by 7V (0.7V×10=7V in a case of serially-connected 10 diodes) or more, a current flows through the PN-junction elements.
In the conventional technique, in both of the bulk MISFET device and the SOI structure FET device, the electrostatic protection circuit is formed from one type of the PN-junction elements and the forward bias voltages are identical to each other. As compared to a protection device having a snap back characteristic, the protection device as PN-junction elements in the forward bias easily satisfy the equation (1) when a power supply voltage is high and a breakdown voltage of an internal circuit element to be protected is sufficiently high.
However, in a product for a low power supply voltage manufactured to have a thin gate insulating film, it is difficult to satisfy the equation (1) even when the PN-junction elements are used for the protection device. In other words, when protection device having one type of forward bias voltage Vf are used, a design margin becomes small.
FIGS. 1A to 1C schematically show a voltage-current characteristic in a case that a plurality of PN-junction elements are serially connected between two terminals and a current (expressed as Di) flows when the forward bias voltage (ESD voltage) is applied between the two terminals. When the design margin is large (Wd1) as shown in FIG. 1A, the n PN-junction elements or (n+1) PN-junction elements can be used. When the design margin is small (Wd2) as shown in FIG. 1B, the size of the PN-junction element is increased (ΔR′) and only k PN-junction elements can be used. If (k+1) PN-junction elements are used, the size must be made very large. This is impossible due to limitation of the chip size.
In FIGS. 1A and 1B, the forward bias voltage Vf of the protection device is located at a proper “position”. However, in an actual product, when one type of Vf (one type even in serial connection) is used, the value of n×Vf in the equation (1) may not be a value near Vdd+α. In such a case, the configuration of (n+1) PN-junction elements cannot satisfy a Vo−β margin sometimes. This state is shown in FIG. 1C. It is noted that FIG. 1C shows m PN-junction elements.
Specifically, a device is considered which has an operation start voltage Vh (the forward bias Vf of the whole of serially connected PN-junction elements) which satisfies the relation of Vh>2.0V (assuming the device with a power supply voltage of about 1.2 to 1.5V), and the breakdown voltage Vo of the internal element or the protection device itself which satisfies the relation of 5V<(Vo−β).
Furthermore, it is assumed that the resistance (per basic area or perimeter) with a predetermined basic size of PN-junction is 100Ω and the resistance is inversely proportional to the size. On the assumption of the HBM test of 2000V, the protection device effective resistance must be equal to or smaller than 3.7Ω according to the equation (3). The resistance value of 3.7Ω is a value in a simplified example and obtained from the following equation:2000V/1500Ω=1.333 ARegarding 1.333 A as 1.34 A,5V/1.34 A≅3.7Ω
Here, it is supposed that the protection device is configured of one type of PN-junction elements. When the forward bias voltage Vf of one PN-junction element is 0.6V, if n=4 and Vh=2.4V,(5V−2.4V)=2.6V/1.34≅1.94Ω, and1.94/4=0.49Ω per PN-junction element 1,which requires the size of about 200 times of the basic element (the size of 204×4=816 times as a whole).
The same also applies to cases of Vf=0.7V and 0.8V
All of these cases are shown in FIG. 2.
In the above-mentioned example, it is found out that Vf of 0.6V requires a large size. Since the resistance r varies depending on Vf in fact, superiority or inferiority cannot be decided based on the above-mentioned simple calculation. Since r generally becomes higher as Vf is smaller, the cases of Vf=0.7V and Vf=0.8V in the above-mentioned example require substantially a same size. According to the conventional technique, although the appropriate PN-junction may be accidentally realized, optimum design cannot be achieved.
In the bulk MOSFET process, when the PN-junction elements are formed without adding a special process, P+/N well junction and N+/P well junction are formed. In both junctions, since both well concentrations and both SD (source/drain) diffusion layers (P+, N+) have substantially the same concentration ratio, the forward bias voltages have substantially a same value. A technique of using two types of PN-junctions (P+/N well junction and N+/P well junction) for the protection device is known in patent literature 2.
According to the technique described in Patent literature 2, two PN-junction elements are serially connected between two terminals in a reverse direction. However, one is not an external terminal, but a signal line. According to the technique described in the patent literature 2, anodes or cathodes of the elements are connected to each other rather than connecting the anode to the cathode. In this example, at least one of the elements has reverse bias. Both of the PN-junction elements of this structure have a well and the concentration of the P well is substantially the same as that of the N well (substantially the same order). Thus, the voltages Vf are nearly the same.
Citation List:
                [patent literature 1]: JP-A-Heisei 10-512718        [patent literature 2]: U.S. Pat. No. 6,329,691        [patent literature 3]: JP 2004-207398A        